ChirayuGCCChirayuGCC
    Vertical Pillar
    Pune
    Bangalore
    Hyderabad

    Semiconductors GCC Setup in India

    Pune, Bangalore, Hyderabad, India's VLSI, EDA and chip-design corridor.

    Front-end design, verification, physical design, DFT, analog/mixed-signal, EDA tool development and post-silicon validation for global fabless and IDM companies.

    Market size
    India semi-design talent: 20% of global headcount
    Talent depth
    85,000+ VLSI engineers; growing 12% YoY
    Cost range
    USD 32 to 60K per FTE

    The India edge for Semiconductors

    Why global enterprises pick India for their Semiconductors GCCs.

    Every major fabless (Nvidia, AMD, Qualcomm, Broadcom, Marvell) has India R&D

    Cadence, Synopsys, Siemens EDA all have major India centres

    India Semiconductor Mission USD 10 Bn incentive

    Pune emerging as analog/mixed-signal and automotive-grade hub

    IIT Bombay, IIT Madras, IIIT Hyderabad VLSI pipeline

    GCC archetypes for Semiconductors

    R&D Centre
    Centre of Excellence
    Innovation Centre
    Engineering Centre

    Primary Indian cities, deep dives

    Technology stack we support

    Cadence Virtuoso
    Synopsys DC/PT
    Siemens Calibre
    SystemVerilog
    UVM
    Python
    TCL
    Perl

    Regulatory & compliance

    ITAR-aware
    EAR-aware
    Automotive ISO 26262
    DO-254

    Frequently asked questions

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